The present invention relates to a semiconductor memory device and a memory system, and principally to a high storage capacity type dynamic RAM (Random Access Memory) and a technique effective for use in a data holding technique employed in a memory system using the dynamic RAM.
There has been known a dynamic RAM wherein an oscillator, having an oscillating period or cycle which varies depending on the temperature, is provided to vary a refresh period or cycle according to a change in temperature, thereby reducing a data holding current that flows during self-refresh. This type of dynamic RAM has been disclosed in Japanese Patent Application Laid-Open No. 5-6663. There has been also known a dynamic RAM of a type wherein a plate voltage applied to each of dynamic memory cells is lowered during self-refresh to reduce a leakage current that flows through the dynamic memory cell. This type of dynamic RAM has been disclosed in the 1995 IEEE international Solid-State Circuit Conference, ISSCC 95/SESSION 14/DRAM/PAPER FA14, 1, xe2x80x9cA Sub-0.5xcexc A/MB DATA-Retention DRAMxe2x80x9d.
In the former dynamic RAM, the oscillator, whose oscillating cycle varies depending on the temperature, automatically sets the optimum refresh cycle with respect to a change in data holding time due to a variation in ambient temperature of the dynamic RAM in order to minimize the data holding current in the self-refresh mode.
Now, the decision of the data holding time of each dynamic memory cell is made to cope with a leakage current developed in a PN junction dependent on structures of a MOSFET and a capacitor both of which constitute each memory or at an interface between a silicon substrate and an oxide film. It has been known that ones of the memory cells in the dynamic RAM, having data holding times that relatively greatly depend on temperatures and a source voltage, command about 0.1% of the number of the entire memory cells. Further, memory cells (hereinafter called xe2x80x9cworst memory cellsxe2x80x9d) of a small number of these memory cells, which are shortest in data holding time, will determine the whole data holding time of the dynamic RAM.
The oscillator, whose cycle varies depending on the temperature, comprises pseudo memory cells composed of about 1000 actual memory cells connected in parallel, a precharge circuit and a comparison circuit for detecting a potential applied to each pseudo memory cell. The oscillator detects an effect of temperatures exerted on the actual memory cells on a simulation basis by detecting, as a drop in the potential of each pseudo memory cell, a decrease in electric charge stored in the pseudo memory cell based on a precharge signal. Therefore, the inventors, et al. of the present application have discovered a problem that since the oscillating period of the oscillator principally follows data holding times of the great majority of memory cells other than the small number of memory cells in the dynamic RAM, the corresponding memory cells are different from the worst memory cells that greatly depend on the temperature and the power source, whereby the optimum refresh cycle cannot be obtained.
The latter dynamic RAM is intended to lower a plate potential applied to each memory cell, which is normally Vcc/2, to Vss (reference potential) upon designation of the self-refresh mode and reduce a potential at a PN junction between capacitor portions of the memory cells. Since, however, a storage node of each memory cell can be lowered to a negative potential by coupling by reducing the plate potential of each memory cell to Vss, it is necessary to reduce the potential at a word line so as to correspond to the negative potential to prevent an address selection MOSFET whose gate is connected to the word line from being turned on. Further, the adverse effect of increasing the time required to return the self-refresh mode to a normal access mode is produced.
An object of the present invention is to provide a semiconductor memory device and a memory system wherein a data holding function with a high degree of reliability can be provided owing to a simple structure. Another object of the present invention is to provide a semiconductor memory device and a memory system both capable of greatly reducing power consumption in a data holding mode (self-refresh mode). The above and other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of featured aspects of the invention disclosed in the present application will now be briefly described. Two memory cells in different memory arrays or dynamic RAMs are simultaneously selected in accordance with the designation of a specific write operation mode so that a logic 1 of a write signal is associated with a state in which an electric charge exists in the corresponding capacitor and a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor, whereby the same write signal is written. Two dynamic memory cells in the different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode so that in correspondence with the write operation, a state in which an electric charge exists in a capacitor of each of the two dynamic memory cells, referred to above, is associated with a logic 1 of a read signal and a state in which no electric charge exists in the capacitor, is associated with a logic 0 of the read signal. Further, a logic 1 level associated with two read signals are preferentially outputted. That is, a logic 1 level is outputted for the read signal under a condition in which either or both of the selected memory cells have an electric charge stored therein indicative of a logic 1 write signal.
According to the aforementioned means, since the data can be read from the other of the two memory cells even if the information stored in one of the two memory cells is destroyed due to the leakage current, by associating the state in which the electric charge exists in each of the capacitors of the two memory cells with the logic 1 in the data holding state or the like and preferentially outputting it, the data can be held with high reliability and the refresh cycle can be made long according to the average memory cell, thus making it possible to greatly reduce power consumption.